1. Field of the Invention
This invention concerns a logic level converting circuit for converting a ECL level signal to a CMOS level signal. More particularly, this invention concerns a logic level converting circuit fabricated using bipolar transistors and complementary MOS (CMOS) circuits.
2. Description of the Prior Art
Recently, a Bi-CMOS circuit, which is composed of bipolar transistors and CMOS circuits, has been widely used for making use of the characteristics of the high speed operation of the ECL circuit and the low power consumption of the CMOS circuits. However, a logic level converting circuit for converting the ECL level (e.g., -0.9 volt to -1.7 volt) signal to a CMOS level (e.g. 0 to -5.2 volt) signal is required.
FIG. 1 is a block diagram of a conventional logic level converting circuit using the Bi-CMOS technology. Namely, the logic level converting circuit includes a receiving circuit section RC, a differential amplifier section DA, an emitter follower circuit section EF and a level shifting section LS.
FIG. 2 is a circuit diagram of the conventional logic level converting circuit. Namely, the receiving circuit section RC includes a bipolar transistor Q1 having a base electrode supplied with a ECL level input signal A, a collector electrode supplied with a power source voltage VCC (e.g., 0 volt) and an emitter electrode connected to the anode of a diode DI. The cathode of the diode DI is connected to a second power source voltage VEE (e.g., -5.2 volt) through a constant current source I1.
The differential amplifier section DA includes differential pair transistors Q2 and Q3. The base electrode of the transistor Q2 is connected to the cathode of the diode DI, and the collector electrode thereof is supplied with the power source voltage VCC through a resistor R1. The base electrode of the transistor Q3 is supplied with a reference voltage V1, and the collector electrode thereof is supplied with the power source voltage VCC through a second resistor R2. The emitter electrodes of the transistors Q2 and Q3 are connected in common and are connected to a constant current source I2. The input signal B to the base electrode of the transistor Q2 is compared with the reference voltage V1, and complementary signals C and C are output from the collector electrodes of the transistors Q2 and Q3, respectively.
The emitter follower circuit section EF includes bipolar transistors Q4 and Q5. The base electrodes of the transistors Q4 and Q5 are connected to the collector electrodes of the transistors Q2 and Q3, and the collector electrodes thereof are supplied with the power source voltage VCC. The emitter electrodes of the transistors Q4 and Q5 are connected to constant current sources I3 and I4, respectively. The complementary signals C and C are level shifted by the transistors Q4 and Q5, and level shifted complementary signals D and D are obtained at the emitter electrodes of the transistors Q4 and Q5.
The level shifting means LS includes two pairs of P-channel MOS (PMOS) transistors P10, P11 and P12, P13. The gate electrodes of the PMOS transistors P11 and P12 are supplied with one of the level shifted complementary signal D, and the gate electrodes of the transistors P10 and P13 are supplied with the remaining signal D. The source electrodes of the PMOS transistors P10, P11, P12 and P13 are supplied with the power source voltage VCC, and the drain electrodes thereof are connected to current mirror circuits M1 and M2.
The current mirror circuit M1 includes N-channel MOS (NMOS) transistors N10 and N11. The source electrodes of the NMOS transistors N10 and N11 are supplied with the power source voltage VEE, and the gate electrodes thereof are connected in common. The drain electrode and the gate electrode of the NMOS transistor N10 are connected to the drain electrode of the PMOS transistor P10. Similarly, the current mirror circuit M2 includes two NMOS transistors N12 and N13. The source electrodes of the NMOS transistors N12 and N13 are supplied with the power source voltage VEE, and the gate electrodes thereof are connected in common. The drain electrode and the gate electrode of the transistor N12 are connected to the drain electrode of the transistor P12, and the drain electrode of the transistor N13 is connected to the drain electrode of the transistor N13 is connected to the drain electrode of the transistor P13.
In this conventional circuit, complementary output signals E and E of the CMOS level can be obtained from the drain electrodes of the transistors P11 and P13. However, in this conventional circuit, two current mirror circuits M1 and M2 are used in the level shifting section LS. Thus, at least one direct current path may be formed between the power sources VCC and VEE in accordance with the complementary signals D and D, and power consumption may be increased. Thus, the advantage of low power consumption provided by utilizing the CMOS circuits may be lost.
Furthermore, the on/off switching of the PMOS transistors P10, P11, P12 and P13 is accomplished by the relationship between the power source voltage VCC and the complementary signals D and D. Thus, due to the fluctuation of the threshold voltages of the PMOS transistors, the PMOS transistors are sometimes insufficiently turned off, and the output signal E and E do not reach the VEE level. Therefore, a through current sometimes flows in a following CMOS circuit (not shown). Thus, the merit of the low power consumption due to the CMOS circuits may be further deteriorated.